Scaling the Aspect Ratio of Nanoscale Closely Packed Silicon Vias by MacEtch: Kinetics of Carrier Generation and Mass Transport

Metal-assisted chemical etching (MacEtch or MaCE) is a robust and versatile process that has been adopted to overcome the limits of conventional semiconductor wet and dry etching technologies.[1–4] The advantage of producing high aspect ratio microand nano-structures with this simple and low-cost process has attracted attention for improving not only the etch quality but also the performance in many kinds of semiconductor device applications including light emitting diodes,[5] solar cells,[6–9] biosensors,[10] supercapacitors,[11] and thermoelectrics.[12] The typical MacEtch process starts by patterning catalysts composed of noble metals (Au, Pt, Pd, Ag, Cu, Ni, etc.)[1,13–20] or graphene[21] on a semiconductor substrate or epitaxial structure. The catalyst layer can be patterned into any arbitrary geometry such as a mesh, dots, or trenches with microor nano-scale dimensions.[22] The substrate with metal patterns is then immersed in a chemical solution of an oxidant (e.g., hydrogen peroxide, H2O2) to oxidize and an acid (e.g., hydrofluoric acid, HF) to selectively etch the semiconductor localized under the patterned catalysts while the metal catalyst descends into the semiconductor. MacEtch of silicon involves a pair of redox reactions: a cathodic reaction and an anodic reaction.[1] The cathodic reaction is the reduction reaction at the liquid/catalyst interface, which transfers the free electrons within the catalyst to the oxidant (H2O2). The anodic reaction is the half-reaction at the catalyst/silicon interface that produces the oxidized silicon by diffusing electrons from silicon to the catalyst, thus injecting holes. This oxidized region generated through hole-injection can then be selectively etched by HF. The method of fabricating pillars or nanowires by MacEtch using interconnected mesh patterned catalyst layers has been well demonstrated, reaching aspect ratios as high as 200 for uniform nanowire arrays.[23–29] The process of fabricating high aspect ratio vias using MacEtch, which requires discrete dot catalyst patterns, is an important technique that can be applied to high density 2.5D/3D memory,[30] interconnects, through silicon vias (TSVs), photonic crystals, detectors, and many other Scaling the Aspect Ratio of Nanoscale Closely Packed Silicon Vias by MacEtch: Kinetics of Carrier Generation and Mass Transport